NASA has selected SiFive, an American chip startup that designs RISC-V CPUs, to provide the “core CPU” for the space agency’s upcoming high-performance computing (HPSC) processor.
NASA announced in June that its HPSC . project It will develop a new aviation computing technology that will feature “at least 100 times” the computational power of current spaceflight computers, which were developed nearly 30 years ago.
These CPUs must be resistant to radiation damage, operate with minimal power, and shut down when not needed, yet still be able to robotically land spacecraft on Mars and support astronauts in space.
The main problem with older spaceflight computers is that they are over-engineered, designed for important parts of more intensive computations, such as during the landing sequence on Mars. They also need to operate with a minimum of electrical power sources.
Engineers from NASA’s Jet Propulsion Laboratory (JPL) are leading the development of HPSC to deliver multi-core chips and their drivers. HPSC must process data 100 times faster than current “space-qualified” computers due to power limitations.
According to SiFiveNASA’s HPSC will use an eight-core SiFive vector core X280 RISC-V and four additional SiFive RISC-V cores.
The chip designer says the X280 demonstrated the 100 times faster speed required for NASA’s HSPC and is good for applications that require high throughput and single-thread performance under power constraints.
“The X280 demonstrates the demands for huge performance gains over competing processor technology, and our SiFive RISC-V IP allows NASA to benefit from the support, resilience, and long-term viability of the rapidly growing global RISC-V ecosystem,” He said Jack Kang, Senior Vice President of Business Development at SiFive.
NASA’s selection of SiFive is a small but significant win for the open-source RISC-V standard (dubbed the “Risk Five”), which UC Berkeley professors David Patterson and Krist Asanovic created 12 years ago.
Developers are free to change the RISC-V (ISA) chip instruction set architecture, which defines how the chip’s hardware works. That makes it different from Intel’s closed x86 ISAs, which dominate computers and servers, and ARM Ltd’s licensed ARM instructions for most smartphone makers, which have proven popular for Apple’s M1 chips for Macs.
per Report from the record in MayRISC-V International President Calista Redmond said the RISC-V laptop will be unveiled this year.
SiFive in March Raised $175 million, worth $2.5 billion. More than $350 million has been raised so far from investors including Intel Capital, SK Hynix and Qualcomm Ventures.
Intel sees some opportunities in RISC-V chips as well after the launch of Intel Foundry Services (IFS) last year and its return to making chips for others. In February, Intel Join RISC-V as a main member Together with IFS, he announced a $1 billion fund to boost ISAs tools across x86, Arm, and RISC-V. And she makes High-performance RISC-V cores from chip startup Ventana Microcro Available through IFS.
NASA JPL in August announced that it has selected Microchip Technology, a developer of US-based industrial control systems to develop his own HPSC processor. Microchip Technology was contracted to design, design and deliver the HPSC processor over a three-year period under a $50 million contract. NASA ad doesn’t mention RISC-V, but Microchip in announced June The industry’s first RISC-V-based Programmable Gate Array (FPGA).
According to Microchip, its design will provide “end-to-end Ethernet networking, advanced artificial intelligence/machine learning processing and communication support” for NASA.