Article written by: Dan Kochbacharin
3D integrated circuits promise a whole new level of power, performance, space and functionality.
As design teams continue to develop new generations of transformative products, the demand for computing remains tough. Modern workloads have brought packaging technologies to the fore for innovation and have pushed the boundaries of silicone product design in terms of product performance, function, and cost. Not long ago, packaging technologies were seen as inconvenient back-end operations. But times have changed, and progress in the fields of artificial intelligence, big data, cloud computing, and Self-driving vehicles It has pushed the envelope of computing unlike ever before (along with the need for packaging technologies).
This computing evolution has led to the shrinking of chips and the emergence of multi-die architectures, creating a promising landscape for 3D silicon stacking and advanced packaging innovation to improve system performance. 3D integrated circuits offer a practical approach that promises a whole new level of power, performance, space and functionality.
However, the right choice of packaging depends on many factors, and designers need help navigating the best path through the many options and styles available. To accelerate the adoption and production of 3D integrated circuits in the future, the semiconductor industry needs a streamlined collaborative ecosystem that can provide best-in-class optimization at the system level.
Looking closely at stacking 3D silicon
Traditionally, the major players in the semiconductor industry, such as EDA, IP, substrate, memory and test vendors, will focus on a single pillar of expertise – without gaining a deep understanding of how their work affects the overall chip integration and compatibility. This means that teams will not only use different front-end tools but will need a common product roadmap and well-defined communication channels between all parties involved. Fundamental shortcomings in the front-end and back-end add to the complexity of the design, requiring more collaboration between players to reduce late integration, increase productivity levels, and enhance system product innovation.
In terms of stacking itself, packing multiple layers of transistors onto different sized chips requires the utmost precision. Unlike in the past, when teams could remove a defective chip on a printed circuit board and replace it with a new one in the testing phase of a system (even if it was stacked), teams could not access the chips once they had been assembled into a 3D structure. If an error occurs, the chip must be thrown and generated again.
Let’s say a foundry releases a new design update for its customers. By the time the client receives the update and releases it to the IP vendors, useful time is lost. To add fuel to the fire, it takes anywhere from six months to a year for the corresponding IP to be ready. During this process, if the EDA vendor in question is not aware of the latest design rule for the foundry, the EDA tool ends up invalid for the latest design update – a difficult situation for everyone involved.
EDA tools rely on interoperability and need complete and comprehensive tools for effective multi-template 3D system integration. While it may be relatively easy to meet single-chip designs, the interaction between chips stacked on top of each other in a 3D IC architecture and for an EDA tool to recognize if a chip is 3D stacked is not easy. .
Accelerate design success
lift Advanced packaging technologies for the integration of heterogeneous wafers It was a clear trend for many applications. With the continuous growth of computing-intensive applications across various industries, 3D IC enables innovation for HPC, automotive, IoT, and mobile use cases.
Domain-specific chiplets offer incredible value to the industry, though they require advanced packaging for teams to have enough options to stack chips upon chips or chips upon chips for higher density, greater functionality, and better performance—all while maintaining the same or smaller footprint.
This opportunity expands the possibilities for industry advancement as it navigates increasing chip complexity and design sizes. Regardless of whether the vendor changes its business model, the integration and packaging of chipsets with multiple layers, multiple chip sizes and multiple functions will be of paramount importance to unlock ultimate design flexibility with high computing power and small form factors.
As a comprehensive family of 3D silicon stacking technologies and advanced encapsulation technologies, TSMC 3DFabric complements the company’s advanced semiconductor technologies to unlock system-wide innovations. Our front-end technologies, or TSMC-SoIC (System on a Chip Integrated), provide the precision and methodologies needed for today’s 3D silicon stacking requirements.
To this end, TSMC customers have a unique perspective when it comes to addressing computing hurdles.
AMD is a leader in 3D stacking silicon, and is one of those customers that has benefited from the dramatic improvements in performance. The company drove the world’s first TSMC-SoIC-based CPUs by working with it TSMC and its Open Innovation Platform (OIP) partners, to accelerate the development of a robust chip stacking ecosystem for future generations of high-performance, energy-efficient chips.
No single customer or partner can enable system-wide innovation of the scale required. Effective collaboration between all chip companies, design partners and foundries in the ecosystem (EDA, IP, DCA/VCA, memory, OSAT, substrate and test) will be critical to unlocking the next step of system integration and product innovation.
Recognizing the need to accelerate 3D IC ecosystem innovation and simplify implementation, TSMC launched the TSMC 3DFabric Alliance in October 2022 as part of the existing TSMC OIP. Clients and design firms can now access the platform to collaborate on best-in-class 3D IC solutions and get designs right the first time with clearer product roadmaps.
This enables the broader ecosystem to develop better 3D IC system designs and achieve faster time to market compared to designing larger monolithic dies – ultimately greatly accelerating 3D IC customer adoption and ecosystem readiness.
As workloads evolve, it is important that packaging and semiconductor technologies advance together. The birth of such collaborative initiatives paves the way for a new and viable era that can handle complex process nodes and provide advanced 3D design solutions for a variety of applications and fields.
Going forward, TSMC expects to see a shift from companies focused solely on chip design to implementing a well-rounded and comprehensive approach around system-wide integration to bring a new level of product innovation alive. In the meantime, we will continue to do our best to open new doors for the industry to continue innovating in this promising space.
This article was originally published E Times.
Dan Kochbacharin is the Head of Design Infrastructure Management at TSMC.